The current, highly competitive semiconductor market is forcing semiconductor companies to constantly seek improvements in productivity by reducing manufacturing time while maintaining or increasing production output. The small feature sizes and the large number of steps required to fabricate state-of-the-art integrated circuits on semiconductor wafers makes it essential that each of the process steps meet a tight set of specifications. Since process variations are inevitable, performance monitoring techniques such as statistical process control (SPC) are commonly used to control fabrication processes. In addition to statistical techniques for controlling process quality, a number of other techniques have been developed to measure the performance of equipment in terms of reliability, availability, maintainability, and utilization of process tools. For example, it is well known to measure tool performance based on status tracking using common indices such as WPH (Wafers Per Hour), MTTR (Mean Time To Repair), MTBF (Mean Time Between Failure), etc. More recently, an industry accepted performance measurement known as OEE (Overall Equipment Effectiveness) has been used as a performance metric which takes into consideration the availability, operational efficiency, rate efficiency and rate of quality when computing the effectiveness of process tools.
Although highly effective in some applications such as a single process tool, these techniques and indices do not lend themselves for effective use in the case of multiple tools that are combined into a single piece of equipment, where the tools are arranged in-line to perform sequential processing steps that are associative. Sequential tools are sometimes referred to as serial tools because they process wafers in a series of sub-steps formed in separate modules or “tool units” of the equipment. One example of combined, associative tools is a so-called scanner and track for carrying out photolithographic processing of the wafers. This process is carried out in three basic steps. First, a photoresist is applied to each wafer in a coater. The wafers are then exposed to a radiation source in a stepper, and finally each exposed wafer is developed in a photoresist developer. Since the IC's are typically multilayered, this process is repeated a number of times. The “track” referred to above includes both a coater and a developer. The scanner, which is combined with the track in a single cluster tool, is used to scan defects in the coated wafers, prior to developing.
In the past, because the scanner and track are formed in a single, combined cluster tool, the traditional indices have been inadequate for analyzing and tracking in-line performance of the equipment. Although computer integrated manufacturing (CIM) techniques are capable of measuring total processing time for wafers flowing through the scanner and track, this collected data provides little information regarding the processing efficiency of individual equipment components (tool units), and the bottlenecks in flow that may exist within the cluster tool.
Accordingly, there is a need in the art for a method of identifying bottlenecks and improving throughput of wafer processing equipment having in-line, associated tools. The present invention is directed towards providing a solution to this problem